Simple Computer (CPU) Design
Coursework · Fall 2025
VerilogComputer ArchitectureAssembly
- Built an assembly program on a custom 16-bit Simple Computer ISA to evaluate transportation options (Car/Plane/Train/Bus) using pointer-based memory reads and sequential traversal.
- Designed and integrated a Verilog-based Simple Computer CPU (datapath + control) to execute the full instruction cycle.
- Computed route metrics and a combined score (TRS): TRS = T + (C×4) + E − (CS×2) + S; stored results in data memory.